EDN

Austriamicrosystems, IBM team for CMOS HV process

MUNICH, Germany — IBM and Austriamicrosystems have agreed to share a jointly developed high voltage CMOS manufacturing process. This will enable both companies as well as their foundry customers to ...
EDN

ST offers networking variant on ISDA 32-nm bulk CMOS

LONDON — European chip company STMicroelectronics NV (Geneva, Switzerland) has announced the availability of a bulk 32-nanometer CMOS manufacturing process and “platform” for the development of ASICs ...
Tom's Hardware on MSN

IBM goes sub-1nm, develops 0.7nm-class technology

It uses two wafers instead of one, along with ultra-thin dielectric bonding ...
Electronic Design

Alliance Produces Ultra-Dense SRAM Cell In 45nm CMOS Technology

The Crolles2 Alliance has described at the VLSI Symposium in Kyoto, Japan, the creation, under production conditions, of six-transistor SRAM-bit cells with an area less than 0.25 square microns—half ...
ExtremeTech

Beyond 7nm and silicon: The first III-V CMOS wafers roll off production lines

Imec, perhaps the world's top semiconductor research center, has created the first monolithic III-V CMOS transistors on 300mm silicon wafers. With current silicon-based transistors hitting a wall at ...
Electronic Design

Ring-Oscillator Process Monitors for Wafer-Level CMOS Screening

Ring-oscillator process monitors give production test teams a fast on-die frequency measurement for identifying CMOS process variation and sorting dies at wafer level. A process monitor is a dedicated ...