TechRepublic

FPGA Implementation of a New Parallel FIR Filter Structures

In recent days filters with large lengths are started to use. So parallel processing is essential at any cost. In this paper, the authors propose new parallel FIR filter structures, which are ...
Hackaday

FIR filter

Digital filters are always an interesting topic, and they are especially attractive with FPGAs. [Pabolo] has been working with them in a series of blog posts. The latest covers an 8th order FIR filter ...
EDN

Analyze DSP designs in FPGAs with the z-transform

Crafting DSP algorithms for optimum performance in hardware often requires sophisticated design techniques, such as pipelining and overclocked control logic. Such is the case for implementations using ...
Nature

FIR Filter Design and Optimization Techniques

The design of finite impulse response (FIR) filters remains a cornerstone of digital signal processing, with ongoing efforts to refine both the algorithmic and hardware aspects of their implementation ...
EDN

EDN Access — 07.04.96 Fastand flexible:FIR filters in reconfigurable logi

Reconfigurable logic lets you implement DSP functions in hardware, providing a mix of speed and design flexibility that isn't available in DSPs or mask-programmed ASICs. Filter-design tools make ...
Nature

FIR Filter Design and VLSI Implementation

The design of Finite Impulse Response (FIR) filters has evolved into a sophisticated discipline that balances signal-processing performance with hardware efficiency. Innovations in FIR filter design ...
Design-Reuse

Mapping LMS Adaptive Filter IP Core to Multiplier-Array FPGA Architecture for High Channel-Density VOIP Line Echo Cancellation

The LMS adaptive filter is the main functional block in high channel-density line echo cancellers for VOIP. In this paper, we describe an LMS adaptive FIR filter IP and estimate its performance when ...